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XQR2V3000-4CG717V宇航级抗辐射芯片

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    XQR2V3000-4CG717V宇航级抗辐射芯片售价:128000元, 受控器件订购:13632710398 sapcelt@126.com

    XQR2V3000-4CG717V宇航级抗辐射芯片

    总结辐射QPo&tade;Vitex-II特性•行业第一辐射FPGA平台解决方案•保证电离总剂量200 k Rad(Si)•封闭免疫让> 160 MeV-cm2 / mg•已在GEO冷门< 1.5 e-6每设备一天可以实现的推荐的冗余实现•mil -脉冲重复频率- 38535(认证合格的制造商清单)•保证全面军事温度范围+ 125°C(-55°C)•0.15&mico;m 8-Laye 0.12&mico;m金属过程高速晶体管•陶瓷和塑料Wie-Bond和倒装芯片网格数组的包•IP-Immesion架构♦密度从1米到6米系统盖茨♦300 + MHz内部时钟速度(推进数据)♦622 + Mb / s I / O(推进数据)•SelectRAM&tade;内存层次结构♦2.5 Mb的RAM dual-pot 18 Kbit块SelectRAM资源♦1 Mb的分布式SelectRAM资源•高性能外部存储器的接口♦DRAM接口——特别提款权/ DDR SDRAM——网络FCRAM——减少延迟DRAM♦存储器接口——特别提款权/ DDR存储器——评估报告存储器♦凸轮接口•算术函数♦专用的18位x 18位乘法器模块♦快有预见性的逻辑链•灵活的逻辑资源♦67584内部寄存器/锁存与时钟启用♦67584(LUTs)或cascadable查找表16位移位寄存器♦宽多路复用器和wide-input功能支持♦水平梯级链和sum-of-poducts支持♦内部3-state用校车接送学生高性能时钟管理电路♦12 DCM(数字时钟管理器)模块-精确的时钟de-skew-灵活的频率合成——高分辨率相转移♦全球16个时钟多路复用器缓冲区•积极互连技术♦第四代分段路由结构♦可预测的、快速的路由延迟,展开独立的•SelectIO&tade;-Ulta技术♦824用户的I / o♦19单端和六个差标准♦可编程的反向电流马马(2 - 24)

    I / O

    ♦Digitall

    Summay of Radiation Hadened QPo&tade; Vitex-II Featues• Industy Fist Radiation Hadened Platfom FPGASolution• Guaanteed total ionizing dose to 200K Rad(Si)• Latch-up immune to LET > 160 MeV-cm2/mg• SEU in GEO upsets < 1.5E-6 pe device day achievablewith ecommended edundancy implementation• Cetified to MIL-PRF-38535 (Qualified ManufactueListing)• Guaanteed ove the full militay tempeatue ange(–55°C to +125°C)• 0.15 &mico;m 8-Laye metal Pocess with 0.12 &mico;mHigh-Speed Tansistos• Ceamic and Plastic Wie-Bond and Flip-Chip GidAay Packages• IP-Immesion Achitectue♦ Densities fom 1M to 6M system gates♦ 300+ MHz intenal clock speed (Advance Data)♦ 622+ Mb/s I/O (Advance Data)• SelectRAM&tade; Memoy Hieachy♦ 2.5 Mb of dual-pot RAM in 18 Kbit blockSelectRAM esouces♦ Up to 1 Mb of distibuted SelectRAM esouces• High-Pefomance Intefaces to Extenal Memoy♦ DRAM intefaces- SDR/DDR SDRAM- Netwok FCRAM- Reduced Latency DRAM♦ SRAM intefaces- SDR/DDR SRAM- QDR SRAM♦ CAM intefaces• Aithmetic Functions♦ Dedicated 18-bit x 18-bit multiplie blocks♦ Fast look-ahead cay logic chains• Flexible Logic Resouces♦ Up to 67,584 intenal egistes/latches with ClockEnable♦ Up to 67,584 look-up tables (LUTs) o cascadable16-bit shift egistes♦ Wide multiplexes and wide-input function suppot♦ Hoizontal cascade chain and sum-of-poductssuppot♦ Intenal 3-state busing

    High-Pefomance Clock Management Cicuity♦ Up to 12 DCM (Digital Clock Manage) modules- Pecise clock de-skew- Flexible fequency synthesis- High-esolution phase shifting♦ 16 global clock multiplexe buffes• Active Inteconnect Technology♦ Fouth geneation segmented outing stuctue♦ Pedictable, fast outing delay, independent of fanout• SelectIO&tade;-Ulta Technology♦ Up to 824 use I/Os♦ 19 single-ended and six diffeential standads♦ Pogammable sink cuent (2 mA to 24 mA) peI/O♦ Digitally Contolled Impedance (DCI) I/O: on-chiptemination esistos fo single-ended I/O standads♦ Diffeential Signaling- 622 Mb/s Low-Voltage Diffeential SignalingI/O (LVDS) with cuent mode dives- Bus LVDS I/O- Lightning Data Tanspot (LDT) I/O with cuentdive buffes- Low-Voltage Positive Emitte-Coupled Logic(LVPECL) I/O- Built-in DDR input and output egistes♦ Popietay high-pefomance Selectlink Technology- High-bandwidth data path- Double Data Rate (DDR) link- Web-based HDL geneation methodology• Suppoted by Xilinx Foundation Seies&tade; and AllianceSeies&tade; Development Systems♦ Integated VHDL and Veilog design flows♦ Compilation of 10M system gates designs♦ Intenet Team Design (ITD) tool• SRAM-based In-System Configuation♦ Fast SelectMAP configuation♦ IEEE 1532 suppot♦ Patial econfiguation♦ Unlimited epogammability♦ Readback capability• 1.5V (VCCINT) Coe Powe Supply, Dedicated 3.3VVCCAUX Auxiliay and VCCO I/O Powe Supplies• IEEE 1149.1 Compatible Bounday-Scan Logic Suppot

    XQR2V3000-4CG717V宇航级抗辐射芯片 售价:128000元, 受控器件订购:13632710398 sapcelt@126.com

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